Verifying VHDL Designs with Multiple Clocks in SMV
نویسندگان
چکیده
The paper considers the problem of model checking real-life VHDLbased hardware designs via their automated transformation to a model verifiable using the SMV model checker. In particular, model checking of asynchronous designs, i.e., designs driven by multiple clocks, is discussed. Two original approaches to compiling asynchronous VHDL designs to the SMV language such that errors possibly arising from the asynchronicity are preserved are proposed. The paper also presents results of experiments with using the proposed methods for verification of several real-life asynchronous components of an FPGA-based router being developed within the Liberouter project.
منابع مشابه
Case Study: Comparison between Conventional VHDL and UVM Test-Benches for a Slave IS Transceiver
In this survey, we prove that the Universal Verification Methodology, UVM, is not only efficient in verifying large-gate-count IP-based System-on-Chip designs, but it is also efficient in verifying small designs, in comparison with the conventional verification techniques, specifically VHDL testbenches. We have built both a UVM verification environment and a VHDL test-bench to verify the operat...
متن کاملSpecification of Control Flow Properties for Verification of Synthesized VHDL Designs
Behavioral speciications in VHDL contain multiple communicating processes. Register level designs synthesized from these speciications contain a data path represented as a netlist and a controller consisting of multiple communicating synchronous nite state machines. These nite state machines together implement the control ow speciied in and implied by the behavioral speciication in VHDL. This p...
متن کاملVerifying Parametrised Hardware Designs Via Counter Automata
The paper presents a new approach to formal verification of generic (i.e. parametrised) hardware designs specified in VHDL. The proposed approach is based on a translation of such designs to counter automata and on exploiting the recent advances achieved in the area of their automated formal verification. We have implemented the proposed translation. Using one of the state-of-the-art tools for ...
متن کاملVerifying IP-Core based System-On-Chip Designs
We describe a methodology for verifying system-on-chip designs. In our methodology, the problem of verifying system-on-chip designs is decomposed into three tasks. First, we verify, once and for all, the standard bus interconnecting IP Cores in the system . The next task is to verify the glue logic, which connects the IP Cores to the buses. Finally, using the verified bus protocols and the IP c...
متن کاملAn Automatic Design Flow from Formal Models to FPGA
SMV [McM93] is a language suitable for integrated circuit design and optimized for formal verification. VHDL [IEE93] is a design format suitable for simulation and synthesis, but poorly designed for formal verification purposes. The contribution of this paper is the integration of the two approaches through the definition of systematic rules to translate SMV programs into VHDL descriptions, pro...
متن کامل